[AK4492]
4. Connection Example with the AK8157A
The AK8157A is the multi clock generater for the audio product with low RMS gitter. MCLK, BCLK and
LRCK are generated by the AK8157A. Connection example of the AK4492 and the external device is as
follows.
e.g. AK8157: Master / External DSP: Slave
MCLK, BCLK and LRCK are generated by the AK8157A.
SDATA for the AK4492 is output from the external DSP in synchronization with BCLK and LRCK.
System rayout should be designed so that a noise interference between VSS and DVSS does not occure.
AK4492
AK8157
Power Supply
6V
BICK
BICK
BICK/BCK/DCLK(J1)
9.6MHz
DSP
SDATA
LRCK
MCLK
SDATA/DINL/DSDL(H1)
LRCK/DINR/DSDR(G1)
SMUTE/CSN(F1)
SLOW/CDTI/SDA(E1)
DIF0/DZFL(D1)
DIF1/DZFR(C1)
DEM0/DSDL(B1)
DVSS(K2)
External
LRCK
MCLK
SDA
VREFHR(A5,A6)
VREFLR(A7,A8)
VCMR(B8)
Regulator Circuit
CLKIN
Micro-
1F
Controller
External
LPF
AOUTRN(A9)
AOUTRP(B9)
AOUTR
VDD1
VSS1
VDD2
0.1F
0.1F
0.1F
Circuit
TVDD(J2)
1F
RSTN
SCL
PDN(H2)
VDDR(C9,C10,D9)
VSSR(D10,E9,E10)
SSLOW/WCK(G2)
TDMO(F2)
SD/CCLK/SCL(E2)
DIF2/CAD0(D2)
HLOAD/I2C(C2)
GAIN/DSDR(B2)
ACKS/CAD1(A2)
DVDD(K3)
CAD1
CAD0
VSSL(F9,F10,G10)
VDDL(G9,H9,H10)
1F
1F
VDD3
External
LPF
0.1F
0.1F
0.1F
AOUTLP(J9)
AOUTLN(K9)
AOUTL
VSS2
VDD4
VSS3
51ohm
MCLK(J3)
Circuit
LDOE(H3)
PSN(D3)
VCML(J8)
VREFLL(L7,K8)
VREFHL(K5,K6)
TDM1(B3)
TDM0/DCLK(A3)
AVDD(K4)
0.1F
External
VSS
0V
AVDD
1.8V
Regulator Circuit
AVSS(J4)
DCHAIN(B4)
INVR(A4)
33kohm
TESTE(B5)
EXTR(J5)
DVSS
0V
DVDD
1.8V
VDD
5V
VSS
0V
1F
DVSS VSS
Figure 75. Circuit Example with AK8157A
016011073-E-00
2016/12
- 97 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
