[AK4492]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD, DVDD,
VDDL and VDDR. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and DVDD
are supplied from digital supply in system. Power lines of VDDL/R should be distributed separately from
the point with low impedance of regulator etc.
When not using the LDO (LDOE pin = “L”), all power supplies (DVDD (1.8V), TVDD and AVDD (3.3V) and
VDDL/R (5V)) should be powered up at the same time or sequentially in the order of 3.3V (TVDD, AVDD),
1.8V (DVDD) and 5V (VDDL/R).
The internal LDO outputs DVDD (1.8V) when the LDOE pin = “H”. 3.3V (TVDD and AVDD) power supplies
must be powered up before or at the same time with 5V (VDDL/R) power supplies when the LDOE pin =
“H”.
AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. Decoupling
capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the full scale of the analog output range.
The VREFHL/R pin is normally connected to VDD, and the VREFLL/R pin is normally connected to the
VSS. The VREFH, VREFL pin should be connected to the noiseless power supply. If not, it is
recommended to connect these pin to an external regulator circuit as shown in Figure 73. In this case, a
tantalum or an electrolytic capacitor (6.8u) should be used between each of the VREFHL and VREFHR
pins, and the VREFLL and VREFLR pins. Digital signal and clock lines should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted coupling into the AK4492.
Low noise 5V (typ.) should be input to the external regulator circuit. If this input voltage has a noise,
attenuate the noise by a 1st order LPF as shown in Figure 73.
No load current may be drawn from the VCML/R pin since VCML/R is a common voltage of analog signals.
+Vop
1st order LPF
Rlp
7
2
3
6
VREFHR
Pin
4
OPA1611
OPA1611
6.8u
Clp
VREFLR
Pin
+5V
+Vop
7
2
3
6
VREFHL
Pin
Rlp
Clp
4
6.8u
VREFLL
Pin
Figure 73. External Regulator Circuit Example
3. Analog Output
The analog outputs are full differential outputs. The differential outputs are summed externally, VAOUT
=
(AOUT+) (AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range of the setting
the GAIN pin = “L” or GC[2] bit = “0” is 2.8Vpp (typ, VREFHL/R VREFLL/R = 5V) centered around VCML
and VCMR voltages. In this case, the output range after summing will be 5.6V (typ.). The output range of
the setting the GAIN pin = “H” or GC[2] bit = “1” is 3.75Vpp (typ.) centered around VCML and VCMR
voltages. In this case, the output range after summing will be 7.5Vpp (typ.). The bias voltage of the external
summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal VAOUT is 0V for 00000000H (@32bit).
The internal switched•capacitor filters attenuate the noise generated by the delta•sigma modulator beyond
016011073-E-00
2016/12
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AKM [ ASAHI KASEI MICROSYSTEMS ]
