[AK4492]
(Ta = 25 C; LDOE pin = “L”, AVDD = TVDD = DVDD = 1.8 V, AVSS = DVSS = VSSL/R = 0 V; VREFHL/R
= VDDL/R = 5.0 V, VREFLL/R = 0V; Input data = 24 bit; BICK = 64 fs; Signal Frequency = 1kHz; Sampling
Frequency = 44.1kHz; 2 Vrms output mode (GC[2:0] bits = “000” or GAIN pin = “L”); Heavy load drive
mode = off(HLOAD bit=“0” or HLOAD pin=“L”); unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL+VDDR
-
-
-
27
1.6
0.4
40
3
1.5
mA
mA
mA
VREFHL+VREFHR
AVDD
TVDD
fs = 44.1 kHz
fs = 96 kHz
fs = 192 kHz
6
9
mA
mA
mA
mA
LDOE pin = “H”
-
-
-
10
18
0.3
15
27
1.5
LDOE pin = “L”
DVDD
fs = 44.1 kHz
fs = 96 kHz
fs = 192 kHz
-
-
-
-
6
10
18
9
mA
mA
mA
mA
LDOE pin = “L”
15
27
55
Total Idd (fs = 44.1 kHz, LDOE pin = “L”)
35.4
Power down (PDN pin = “L”)
(Note 19)
-
0.4
100
A
TVDD + AVDD + VDDL + VDDR + DVDD
Note 19. In power down mode, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held to DVSS.
Note 20. The DVDD pin becomes an output pin when the LDOE pin = “H”.
016011073-E-00
2016/12
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
