[AK4438]
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling rate is set by DFS2-0 bits (Table 1). The
MCLK frequency corresponding to each sampling speed should be provided externally (Table 2, Table 3).
The AK4438 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0 bits are
changed, the AK4438 should be reset by RSTN bit.
DFS2
DFS1
DFS0
Sampling Speed Mode (fs)
(default)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Speed Mode
8kHz~48kHz
48kHz~96kHz
96kHz~192kHz
N/A
Double Speed Mode
Quad Speed Mode
N/A
Oct Speed Mode
Hex Speed Mode
384kHz
768kHz
N/A
N/A
N/A
N/A
(N/A: Not Available)
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
MCLK(MHz)
Sampling
Speed
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
48fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
64fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
8.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384.0kHz
768.0kHz
Normal
Double
Quad
24.576 36.864
N/A N/A
Oct
Hex
24.576 36.864
Table 2. System Clock Example (Manual Setting Mode)
LRCK
MCLK(MHz)
Sampling
Speed
fs
8.0kHz
128fs
N/A
192fs
N/A
256fs
2.0480
384fs
3.0720
512fs
4.0960
768fs
6.1440
N/A
N/A
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384.0kHz
768.0kHz
Normal
N/A
N/A
N/A
N/A
22.5792 33.8688
24.5760 36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
22.5792 33.8688
24.5760 36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
Hex
Table 3. System Clock Example (Manual Setting Mode)
016001925-E-00
2016/03
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
