[AK4438]
12. Functional Descriptions
■ System Clock
The external clocks which are required to operate the AK4438 are MCLK, LRCK and BICK. MCLK should
be synchronized with LRCK and BICK but the phase is not critical. There are two methods to set MCLK
frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS2-0 bit
(Table 1). The frequency of MCLK at each sampling speed is set automatically (Table 2, Table 3). In Auto
Setting Mode (ACKS bit= “1”), as MCLK frequency is detected automatically (Table 4) and the internal
master clock attains the appropriate frequency (Table 5), so it is not necessary to set DFS2-0 bits.
After exiting reset at power-up (PDN pin = “L” →“H”), the AK4438 is in power-down mode until MCLK and
LRCK are input. The AK4438 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When
changing the clock, the AK4438 must be reset by the PDN pin or RSTN bit.
If the clock is stopped, a click noise occurs when restarting the clock. Mute the digital output externally if
the click noise affects system applications.
016001925-E-00
2016/03
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
