[AK4425A]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and it is enabled or disabled
by DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always OFF.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
(default)
48kHz
32kHz
Table 7. De-emphasis Filter Control (Normal Speed Mode)
■ Analog Output Block
The internal negative power supply generation circuit (Figure 9) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4425A to output an audio signal centered at VSS (0V, typ) as shown in Figure 10. The negative
power generation circuit (Figure 9) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS1 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4425A is placed in the reset mode automatically and the
analog outputs settle to VSS (0V, typ).
AK4425
VDD
Charge
Pump
Negative Power
CP
CN
VEE
VSS1
Cb
(+)
1uF
(+)
Ca
1uF
Figure 9. Negative Power Generation Circuit
AK4425
2.2Vrms
0V
AOUTR
(AOUTL)
Figure 10. Audio Signal Output
MS1127-E-01
2011/03
- 15 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
