[AK4425A]
■ System Reset
The AK4425A is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped
up. The AK4425A is in power-down mode until LRCK are input.
tW<20ms
Power Supply0.8xVDD
0.3V
(VDD, AVDD)
(1)
Low
MCLK
20 µs
Reset Release
(3)
Internal
Reset
50ms(max)
(2)
Reset
Audio circuit
Power-up
Power-up
2, 3
LRCK Clocks
(4)
Power down
Charge Pump
Circuit
Time A
(5)
VEE Pin
0V
0V
“0” data
D/A In
(Digital)
D/A Out
(Analog)
Active (D/A Out)
MUTE (D/A Out)
Notes:
(1) The AK4425A includes an internal Power on Reset Circuit which is used reset the digital logic into a default state after
power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec.
(2) Register writings are valid after 50ms (max).
(3) When internal reset is released, approximately 20us after a MCLK input, the internal analog circuit is powered-up.
(4) The digital circuit and charge pump circuit are powered-up in 2, 3 LRCK cycle when the analog circuit is powered-up.
(5) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/(fs x 16): Normal speed mode
Time A = 1024/(fs x 8): Double speed mode
Time A = 1024/(fs x 4): Quad speed mode
Figure 12. System Reset Diagram
MS1127-E-01
2011/03
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
