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AK4425AET 参数 Datasheet PDF下载

AK4425AET图片预览
型号: AK4425AET
PDF下载: 下载PDF文件 查看货源
内容描述: 192kHz的24位立体声DAC ΔΣ具有2Vrms的输出 [192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 27 页 / 393 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4425A]  
OPERATION OVERVIEW  
System Clock  
The external clocks required to operate the AK4425A are MCLK, LRCK and BICK. The master clock (MCLK) should be  
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the  
delta-sigma modulator. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There  
are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set  
by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2) When the power  
applied, the AK4425A is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is  
detected automatically (Table 3), and the internal master clock becomes the appropriate frequency (Table 4), it is not  
necessary to set DFS0/1.  
The AK4425A is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal  
operation mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the  
AK4425A is powered up. After power-up, the AK4425A is in the power-down mode until MCLK, LRCK and BICK are  
input.  
DFS1  
DFS0  
Sampling Rate (fs)  
(default)  
0
0
1
0
1
0
Normal Speed Mode  
8kHz~48kHz  
60kHz~96kHz  
120kHz~192kHz  
Double Speed Mode  
Quad Speed Mode  
Table 1. Sampling Speed (Manual Setting Mode)  
LRCK  
(kHz)  
fs  
BICK  
(MHz)  
64fs  
Sampling  
Speed  
MCLK (MHz)  
DFS1 DFS0  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
1152fs  
0
0
0
0
0
1
1
0
0
0
1
1
0
0
32.0  
44.1  
48.0  
88.2  
96.0  
-
-
-
-
-
-
8.1920  
12.2880 16.3840 24.5760 36.8640  
2.0480  
2.8224  
3.0720  
5.6448  
6.1440  
11.2896  
12.2880  
Normal  
11.2896 16.9344 22.5792 33.8688  
12.2880 18.4320 24.5760 36.8640  
-
-
-
-
-
-
11.2896 16.9344 22.5792 33.8688  
12.2880 18.4320 24.5760 36.8640  
22.5792 33.8688  
24.5760 36.8640  
-
-
-
-
-
-
-
-
Double  
Quad  
176.4  
192.0  
-
-
-
-
Table 2. System Clock Example  
MCLK  
1152fs  
Sampling Speed  
Normal (fs=32kHz only)  
512fs  
256fs  
128fs  
768fs  
384fs  
192fs  
Normal  
Double  
Quad  
Table 3. Sampling Speed(Auto Setting Mode: Default)  
MS1127-E-01  
2011/03  
- 11 -  
 
 
 
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