[AK4425A]
DC CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
VIH
VIL
min
2.2
-
typ
max
-
0.8
Units
V
V
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
-
-
-
Iin
-
± 10
μA
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Master Clock Frequency
Symbol
fCLK
dCLK
min
2.048
30
Typ
11.2896
max
36.864
70
Units
MHz
%
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
8
48
96
kHz
kHz
kHz
%
32
fsq
120
45
192
55
Duty Cycle
Audio Interface Timing
BICK Period
Duty
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
30
20
20
20
20
SDTI Setup Time
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
MS1127-E-01
2011/03
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
