[AK4426]
DC CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5
∼
+5.5V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Symbol
VIH
VIL
Iin
min
2.2
-
-
typ
-
-
-
max
-
0.8
±
10
Units
V
V
μA
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5
∼
+5.5V)
Parameter
Symbol
min
Typ
fCLK
2.048
11.2896
Master Clock Frequency
dCLK
30
Duty Cycle
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
32
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
tBCK
1/128f
Normal Speed Mode
tBCK
sn
Double Speed Mode
tBCK
1/64fs
Quad Speed Mode
tBCKL
d
BICK Pulse Width Low
tBCKH
1/64fs
Pulse Width High
tBLR
q
BICK “↑” to LRCK Edge (Note
tLRB
30
LRCK Edge to BICK “↑” (Note
tSDH
30
SDTI Hold Time
tSDS
20
SDTI Setup Time
20
20
20
Control Interface Timing (I2C Bus)
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. I
2
C-bus is a trademark of NXP B.V.
Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
max
36.864
70
48
96
192
55
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
MS1176-E-02
-8-
2011/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
