[AK4426]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4426 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register
00H), the sampling speed is set by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2) When the power applied, the AK4426 is in Auto Setting Mode. In Auto Setting Mode (ACKS =
“1”: Default), as MCLK frequency is detected automatically (Table 3) and the internal master clock becomes the
appropriate frequency (Table 4), it is not necessary to set DFS0/1.
The AK4426 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation
mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4426 is
powered up. After power-up, the AK4426 is in the power-down mode until MCLK, LRCK and BICK are input.
DFS1
DFS0
Sampling Rate (fs)
(default)
0
0
1
0
1
0
Normal Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Double Speed Mode
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz)
fs
BICK
(MHz)
64fs
Sampling
Speed
MCLK (MHz)
DFS1 DFS0
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
0
0
0
0
0
1
1
0
0
0
1
1
0
0
32.0
44.1
48.0
88.2
96.0
-
-
-
-
-
-
8.1920
12.2880 16.3840 24.5760 36.8640
2.0480
2.8224
3.0720
5.6448
6.1440
11.2896
12.2880
Normal
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
-
-
-
-
-
-
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688
24.5760 36.8640
-
-
-
-
-
-
-
-
Double
Quad
176.4
192.0
-
-
-
-
Table 2. System Clock Example (Manual Setting Mode)
MCLK
1152fs
Sampling Speed
Normal (fs=32kHz only)
Normal
512fs
256fs
128fs
768fs
384fs
192fs
Double
Quad
Table 3. Sampling Speed(Auto Setting Mode: Default)
MS1176-E-02
2011/03
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