[AK4397]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data=24bit;
R
L
≥
1kΩ; BICK=64fs; Input Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth =
20Hz ~ 20kHz; External Circuit: Figure 18; unless otherwise specified.)
Parameter
min
typ
max
Units
Resolution
-
-
24
Bits
Dynamic Characteristics
0dBFS
-
−103
−93
dB
fs=44.1kHz
THD+N
BW=20kHz
-
−57
-
dB
−60dBFS
0dBFS
-
−100
-
dB
fs=96kHz
BW=40kHz
-
−54
-
dB
−60dBFS
0dBFS
−100
-
dB
fs=192kHz
BW=40kHz
−60dBFS
−54
-
dB
BW=80kHz
−51
-
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted)
114
120
dB
S/N (A-weighted)
114
120
dB
Interchannel Isolation (1kHz)
100
110
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.15
0.3
dB
Gain Drift
-
20
-
ppm/°C
Output Voltage
±2.65
±2.8
±2.95
Vpp
Load Capacitance
-
-
25
pF
Load Resistance
1
-
-
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
-
32
47
mA
-
21
-
mA
DVDD (fs
≤
96kHz)
-
27
41
mA
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+DVDD
-
10
100
μA
Power Supply Rejection
-
50
-
dB
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. By Figure 18. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data.
Note 7. By Figure 18. External LPF Circuit Example 2. S/N does not depend on input bit length.
Note 8. The voltage on (VREFHL/R
−
VREFLL/R) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R
−
VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)
−
(AOUT−) =
±2.8Vpp ×
(VREFHL/R
−
VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 1 kΩ (min) with DC cut capacitor. Please refer to Figure 18. DC load is
1.5kΩ (min) without DC cut capacitor. Please refer to Figure 17. Load Resistance value defines apposite to
ground voltage. Analog performance is sensitive to capacitive load that is connected output pin. Therefore
capacitive load must be minimized.
Note 11. In the power-down mode. P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.
Note 12. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFHL/R pin is held +5V.
MS0616-E-00
-8-
2007/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
