[AK4397]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
dCLK
7.7
40
41.472
60
MHz
%
Duty Cycle
LRCK Frequency
(Note 17)
Normal Speed Mode
fsn
fsd
fsq
30
54
108
45
54
108
216
55
kHz
kHz
kHz
%
Double Speed Mode
Quad Speed Mode
Duty Cycle
Duty
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
1/128fn
1/64fd
1/64fq
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
30
(Note 18)
(Note 18)
20
tLRB
20
tSDH
tSDS
20
SDATA Setup Time
20
DSD Audio Interface Timing
DCLK Period
tDCK
tDCKL
tDCKH
tDDD
1/64fs
160
ns
ns
ns
ns
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
160
(Note 19)
−20
20
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
200
80
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
80
CDTI Setup Time
50
CDTI Hold Time
tCDH
tCSW
tCSS
50
CSN High Time
150
50
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 20)
tPD
150
ns
Note 17. When the normal/double/quad speed modes are switched, AK4397 should be reset by PDN pin or RSTN bit.
Note 18. BICK rising edge must not occur at the same time as LRCK edge.
Note 19. DSD data transmitting device must meet this time.
Note 20. The AK4397 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
the AK4397 should be reset by RSTN bit.
MS0616-E-00
2007/05
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
