ASAHI KASEI
[AK4395]
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Symbol
VIH
VIL
min
2.2
-
typ
-
-
max
-
0.8
Units
V
V
VOH
DVDD-0.5
-
-
V
High-Level Output Voltage (Iout = -100µA)
VOL
-
-
0.5
V
Low-Level Output Voltage (Iout = 100µA)
Input Leakage Current
(Note 17)
Iin
-
-
µA
±
10
Note: 17. DFS0/CAD0, CKS1/CAD1 and P/S pins have internal pull-down or pull-up devices, nominally 100kΩ.
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; C
L
= 20pF)
Parameter
Master Clock Timing
Frequency
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
Serial Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 18)
fsn
fsd
fsq
Duty
30
60
120
45
54
108
216
55
kHz
kHz
kHz
%
Symbol
fCLK
dCLK
min
7.7
40
typ
max
41.472
60
Units
MHz
%
(Note 19)
(Note 19)
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
1/128fs
1/64fs
1/64fs
30
30
20
20
20
20
200
80
80
50
50
150
50
50
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 20)
tPD
Notes: 18. When the normal/double/quad speed modes are switched, AK4395 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4395 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS1-0 change, the AK4395 should be reset by PDN pin or RSTN bit.
MS0040-E-00
-8-
2000/7
AKM [ ASAHI KASEI MICROSYSTEMS ]
