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AK4395VFP 参数 Datasheet PDF下载

AK4395VFP图片预览
型号: AK4395VFP
PDF下载: 下载PDF文件 查看货源
内容描述: [D/A Converter, 1 Func, Serial Input Loading, PDSO28, 0.65 MM PITCH, PLASTIC, VSOP-28]
分类和应用:
文件页数/大小: 26 页 / 278 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4395]  
OPERATION OVERVIEW  
n System Clock  
The external clocks, which are required to operate the AK4395, are MCLK, LRCK and BICK. The master clock (MCLK)  
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation  
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =  
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). CKS0/1/2 set the frequency of MCLK at each sampling  
speed (Table 2). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 6),  
and the internal master clock becomes the appropriate frequency, it is not necessary to set DFS0/1 and CKS0/1/2. In  
parallel mode, CKS2 and DFS1 are fixed to “0”.  
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4395 is in normal operation  
mode (PD = “H”). If these clocks are not provided, the AK4395 may draw excess current because the device utilizes  
dynamic refreshed logic internally. If the external clocks are not present, the AK4395 should be in the power-down mode  
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4395 is in power-down mode  
until MCLK and LRCK are input.  
DFS1  
DFS0  
Sampling Rate (fs)  
Default  
0
0
1
0
1
0
Normal Speed Mode  
30kHz~54kHz  
60kHz~108kHz  
120kHz~216kHz  
Double Speed Mode  
Quad Speed Mode  
Table 1. Sampling Speed (Manual Setting Mode)  
Mode  
CKS2  
CKS1  
CKS0  
Normal  
Double  
Quad  
Default  
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256fs  
256fs  
384fs  
384fs  
512fs  
512fs  
768fs  
768fs  
128fs  
256fs  
192fs  
384fs  
256fs  
N/A  
N/A  
N/A  
N/A  
N/A  
128fs  
N/A  
192fs  
N/A  
384fs  
N/A  
Table 2. System Clocks (Manual Setting Mode)  
Note: The master clock at quad speed supports only 128fs or 192fs.  
LRCK  
fs  
32.0kHz  
MCLK  
BICK  
64fs  
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz  
256fs  
384fs  
512fs  
768fs  
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz  
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz  
Table 3. System clock example (Normal Speed Mode @Manual Setting Mode)  
MS0040-E-00  
2000/7  
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