ASAHI KASEI
[AK4386]
(2) Power save by MCLK stop (PDN pin = “H”)
(1)
PDN pin
Internal
State
Power-down
Power-down
Normal Operation
Power-save
Normal Operation
D/A In
(Digital)
(3)
GD
GD
(2)
(2)
(4)
(5)
(4)
Hi-Z
VCOM
D/A Out
(Analog)
(4)
(5)
Clock In
MCLK, BICK, LRCK
MCLK Stop
External
MUTE
(6)
(6)
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7mF is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section
can be reduced.
(4) Click noise occurs in 3 ~ 4LRCK at both edges (• ¯) of PDN signal, MCLK inputs and MCLK stops. This noise is
output even if “0” data is input.
(5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 6. Power-down/up sequence example 2
MS0280-E-00
2003/12
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
