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AK4386VT 参数 Datasheet PDF下载

AK4386VT图片预览
型号: AK4386VT
PDF下载: 下载PDF文件 查看货源
内容描述: 100DB 96KHZ 24位2CH [100DB 96KHZ 24 BIT 2CH]
分类和应用:
文件页数/大小: 16 页 / 130 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4386]  
OPERATION OVERVIEW  
n System Clock  
The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK)  
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation  
filter and the delta•sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK  
automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1).  
The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin  
= “H”) (Table 2).  
The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin  
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After  
exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input.  
When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin.  
Mode  
Normal Speed  
Double Speed  
Half Speed  
Auto  
DFS1  
L
L
H
H
DFS0  
fs  
MCLK Frequency  
256/384/512/768fs  
128/192/256/384fs  
512/768/1024/1536fs  
Table 2  
L
H
L
8 ~ 48kHz  
48 ~ 96kHz  
8 ~ 24kHz  
8 ~ 96kHz  
H
Table 1. System Clock Example  
MCLK Frequency  
512/768fs  
128/192/256/384fs  
1024/1536fs  
Sampling Speed Mode  
Normal Speed  
fs  
8 ~ 48kHz  
48 ~ 96kHz  
8 ~ 24kHz  
Double Speed  
Half Speed  
Table 2. Auto Mode  
n Audio Interface Format  
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four  
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of  
BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ³ 48fs or BICK = 32fs.  
Mode  
DIF1  
L
L
H
H
DIF0  
L
H
L
H
SDTI Format  
16bit, LSB justified  
24bit, LSB justified  
24bit, MSB justified  
16/24bit, I2S Compatible  
BICK  
³ 32fs  
³ 48fs  
Figure  
0
1
2
3
Figure 1  
Figure 2  
Figure 3  
Figure 4  
³ 48fs  
³ 48fs or 32fs  
Table 3. Audio Interface Format  
MS0280-E-00  
2003/12  
- 9 -  
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