ASAHI KASEI
[AK4386]
(1) Power down by PDN pin
PDN
(1)
Internal
State
Normal Operation
Power-down
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(2)
(2)
(4)
(3)
(4)
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
(5)
Don’t care
External
MUTE
(6)
Mute ON
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7mF is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) When PDN pin = “L”, the analog output is Hi-Z.
(4) Click noise occurs in 3 ~ 4LRCK at both edges (• ¯) of PDN signal. This noise is output even if “0” data is input.
(5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 5. Power-down/up sequence example 1
MS0280-E-00
2003/12
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
