[AK4372]
Addr Register Name
01H PLL Control
R/W
D7
FS3
R/W
1
D6
FS2
R/W
0
D5
FS1
R/W
0
D4
FS0
R/W
0
D3
PLL3
R/W
0
D2
PLL2
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
Default
FS3-0: Select Sampling Frequency
PLL mode: Table 5
EXT mode: Table 11
PLL4-0: Select PLL Reference Clock
PLL mode: Table 3
EXT mode: PLL4-0 bits are disabled
(PLL4 bit is D7 bit of 02H.)
Addr Register Name
02H Clock Control
D7
PLL4
R/W
0
D6
D5
M/S
R/W
0
D4
MCKAC
D3
BF
R/W
0
D2
PS0
R/W
0
D1
PS1
R/W
0
D0
MCKO
R/W
0
0
RD
0
R/W
Default
R/W
0
MCKO: Control of MCKO signal
0: Disable (default)
1: Enable
PS1-0: MCKO Frequency
PLL mode: Table 9
EXT mode: Table 12
BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored.
0: 32fs (default)
1: 64fs
MCKAC: MCKI Input Mode Select
0: CMOS input (default)
1: AC coupling input
M/S: Select Master/Slave Mode
0: Slave mode (default)
1: Master mode
PLL4-0: Select PLL Reference Clock
PLL3-0 bits are D3-0 bits of 01H.
MS0684-E-02
2008/12
- 53 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
