[AK4372]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Master Clock Input Timing
Frequency (PLL mode)
(EXT mode)
Pulse Width Low (Note 22)
Pulse Width High (Note 22)
AC Pulse Width (Note 23)
LRCK Timing
fCLK
fCLK
tCLKL
tCLKH
tACW
11.2896
2.048
0.4/fCLK
0.4/fCLK
18.5
-
-
-
-
-
27
24.576
MHz
MHz
ns
ns
ns
-
-
-
Frequency
Duty Cycle: Slave Mode
Master Mode
fs
Duty
Duty
8
45
-
44.1
-
50
48
55
-
kHz
%
%
MCKO Output Timing (PLL mode)
Frequency
fCLKO
dMCK
dMCK
0.256
40
-
-
-
33
12.288
60
-
MHz
%
%
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
(fs=32kHz, PS1-0= “00”)
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode, PLL4-0 bits = “01110”)
(PLL Mode, PLL4-0 bits = “01111”)
BICK Pulse Width Low
tBCK
tBCK
tBCK
312.5 or 1/(64fs)
-
1/(32fs)
ns
ns
ns
-
-
1/(32fs)
1/(64fs)
-
-
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode,
PLL4-0 bit = “01110”, “01111”)
BICK Pulse Width High
tBCKL
tBCKL
100
-
-
-
-
ns
ns
0.4 x tBCK
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode,
tBCKH
100
-
-
ns
PLL4-0 bit = “01110”, “01111”)
LRCK Edge to BICK “↑” (Note 26)
BICK “↑” to LRCK Edge (Note 26)
SDATA Hold Time
tBCKH
tLRB
tBLR
tSDH
tSDS
0.4 x tBCK
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
50
50
50
50
SDATA Setup Time
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
BICK Duty
BICK “↓” to LRCK
SDATA Hold Time
fBCK
fBCK
dBCK
tMBLR
tSDH
-
-
-
64fs
32fs
50
-
-
-
-
-
50
-
Hz
Hz
%
ns
ns
ns
−50
50
50
SDATA Setup Time
tSDS
-
-
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 27)
CCLK “↑” to CSN Edge (Note 27)
tCSH
MS0684-E-02
2008/12
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
