ASAHI KASEI
[AK4370]
3) LIN1/RIN1/LIN2/RIN2 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL,
RIN1HR, RIN2HR bits
(3) >0s
PMHPL/R bits
MUTEN bit
(5) >2ms
(5) >2ms
(4)
(Hi-Z)
LIN1/RIN1/
LIN2/RIN2 pins
(Hi-Z)
(6)
(7)
(6)
HPL/R pins
Figure 26. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2 and HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1HL, LIN2HL, RIN1HR and RIN2HR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LIN1HL, LIN2HL, RIN1HR or RIN2HR bit is changed to “1”, LIN1, RIN1, LIN2 or RIN2 pin is biased to
0.475 x AVDD.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after LIN1HL, LIN2HL, RIN1HR and RIN2HR bits are changed to “1”.
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the LIN1HL,
LIN2HL, RIN1HR and RIN2HR bits should be changed to “0”.
MS0595-E-00
2007/03
- 32 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
