ASAHI KASEI
[AK4370]
■ Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LIN1L, RIN1L, LIN2L and RIN2L bits control each path switch of LOUT. DARR, LIN1R,
RIN1R, LIN2R and RIN2R bits control each path switch of ROUT. When L1M = L2M bits = “0”, LOG bit = “0” (R1L
R2L = RDL = 100k) and ATTS3-0 bits is “0FH”(0dB), the mixing gain is 0dB(typ) for all paths. When the LOG bit =
=
“1”(RDL= 50k), the DAC path gain is +6dB. When L1M = L2M bits = “1”, LIN1/RIN1 and LIN2/RIN2 signals are output
from LOUT/ROUT pins as (L+R)/2, respectively (R1L = R2L = 200k).
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 39 shows the external bias circuit example.
R1L
LIN1 pin
LIN1L bit
R1L
RIN1 pin
RIN1L bit
R2L
LIN2 pin
LIN2L bit
R2L
100k(typ)
RIN2 pin
RL
RIN2L bit
DALL bit
RDL
RL
DAC Lch
−
+
−
+
LOUT pin
R1L
LIN1 pin
RIN1 pin
LIN2 pin
RIN2 pin
LIN1R bit
R1L
R2L
RIN1R bit
LIN2R bit
R2L
100k(typ)
RL
RIN2R bit
DARR bit
RDL
RL
DAC Rch
−
+
−
+
ROUT pin
Figure 22. Summation circuit for stereo line output
MS0595-E-00
2007/03
- 28 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
