ASAHI KASEI
[AK4370]
4) LIN1/RIN1/LIN2/RIN2 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
(3) >0s
LIN1L, RIN1R,
LIN2L, RIN2R bits
PMLO bit
(5) >2ms
(5) >2ms
(4)
(Hi-Z)
LIN1/RIN1/
LIN2/RIN2 pins
(Hi-Z)
LMUTE,
10H(MUTE)
(Hi-Z)
0FH(0dB)
ATTS3-0 bits
(6)
(Hi-Z)
(6)
(6)
LOUT/ROUT pins
Figure 27. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2 and Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1L, LIN2L, RIN1R and RIN2R bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LIN1L, LIN2L, RIN1R or RIN2R bit is changed to “1”, LIN1, RIN1, LIN2 or RIN2 pin is biased to 0.475 x
AVDD.
(5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1L,
LIN2L, RIN1R and RIN2R bits are changed to “1”.
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
MS0595-E-00
2007/03
- 33 -