ASAHI KASEI
[AK4370]
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”) Power Down (PMDAC bit = “0”)
MCKI pin Refer to Table 2
Input or fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
BICK pin Input
LRCK pin Input
Table 4. Clock Operation in Slave mode
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by using higher
frequency for MCKI. Table 5 shows DR and S/N when the DAC output is to the HP-amp.
DR, S/N (BW=20kHz, A-weight)
MCKI
fs=8kHz
56dB
75dB
fs=16kHz
75dB
90dB
256fs/384fs/512fs
768fs/1024fs
Table 5. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V)
MS0595-E-00
2007/03
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AKM [ ASAHI KASEI MICROSYSTEMS ]
