ASAHI KASEI
[AK4370]
The external clocks required to operate the AK4370 in slave mode are MCKI, LRCK and BICK (Figure 12). The master
clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter.
All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4370 may draw excessive current and will not operate
properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the
DAC should be placed in power-down mode (PMDAC bit = “0”).
AK4370
DSP or μP
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
32fs ~ 64fs
1fs
SDTO
SDATA
Figure 12. Slave Mode
FS0
Mode
0
1
2
FS3
0
0
FS2
0
0
0
FS1
fs
MCKI
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
1024fs
384fs
768fs
N/A
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
N/A
0
4
5
6
0
0
0
1
1
1
8
9
1
1
1
0
0
0
Default
10
12
13
Others
1
1
1
1
Others
Table 2. Relationship between Sampling Frequency and MCKI Frequency
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
MCKI pin Refer to Table 2
BICK pin BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
Power Down (PMDAC bit = “0”)
Input or fixed to “L” or “H” externally
“L”
LRCK pin Output
“L”
Table 3. Clock Operation in Master mode
MS0595-E-00
2007/03
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
