ASAHI KASEI
[AK4370]
OPERATION OVERVIEW
■ System Clock
The AK4370 supports both master and slave modes to interface with external devices. (See Table 1).
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4370 is power-down mode (PDN pin = “L”) and exits reset state, the AK4370 is slave mode. After exiting reset state,
the AK4370 goes to master mode by changing M/S bit = “1”.
When the AK4370 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK4370 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
1
Mode
MCKI pin
BICK pin
Output
(Selected by BF bit)
Input
LRCK pin
Output
(1fs)
Figure
Master Mode
Selected by FS3-0 bits
Figure 11
Input
(1fs)
default
0
Slave Mode
Selected by FS3-0 bits
Figure 12
(32fs ∼ 64fs)
Table 1. Clock Mode Setting (x: Don’t care)
The frequency of master clock inputted to the MCKI pin can be selected FS3-0 bits. (Refer to Table 2)
If the sampling frequency is changed during normal operation of the DAC (PMDAC bit = “1”), the change should occur
after the input is muted by SMUTE bit = “1”, or the input is set to “0” data.
LRCK and BICK are output from the AK4370 in master mode (Figure 11). The clock input to the MCKI pin should
always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the
AK4370 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic
refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit =
“0”).
AK4370
DSP or μP
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
32fs, 64fs
1fs
SDTO
SDATA
Figure 11. Master Mode
MS0595-E-00
2007/03
- 16 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
