ASAHI KASEI
[AK4367]
DC CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
Symbol
VIH
VIL
VAC
VOL
Iin
min
typ
max
-
30%DVDD
Units
V
V
Vpp
V
µA
-
-
-
-
-
70%DVDD
-
1.0
-
(Note 16)
-
0.4
±10
Low-Level Output Voltage
Input Leakage Current
(Iout = 3mA)
(Note 17)
-
Note 16. Only MCLK pin. (Figure 33)
Note 17. I2C pin has internal pull-down device, nominally 100kΩ.
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
tCLKL
tCLKH
tACW
2.048
0.4/fCLK
0.4/fCLK
20
-
-
-
-
24.576
MHz
ns
ns
Pulse Width Low
Pulse Width High
AC Pulse Width
(Note 18)
(Note 18)
(Note 21)
-
-
-
ns
LRCK Timing
Frequency
Duty Cycle:
fs
Duty
8
45
44.1
-
48
55
kHz
%
Serial Interface Timing (Note 19)
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
1/(64fs)
130
130
50
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDATA Hold Time
(Note 20)
(Note 20)
50
50
SDATA Setup Time
tSDS
50
-
-
ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Note 18. Except AC coupling.
Note 19. Refer to “Serial Data Interface”.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
MS0247-E-02
2005/10
- 9 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
