[AK4359A]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; CL = 20pF)
Parameter
Master Clock Frequency
Symbol
fCLK
dCLK
min
2.048
40
typ
11.2896
max
36.864
60
Units
MHz
%
Duty Cycle
LRCK Frequency
Normal Mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
fsq
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
Duty Cycle
Duty
TDM256 mode (TDM0= “1”, TDM1= “0”)
Normal Speed Mode
High time
fsn
tLRH
tLRL
8
48
kHz
ns
ns
3/256fs
3/256fs
Low time
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
Double Speed Mode
High time
fsn
fsd
tLRH
tLRL
8
60
3/128fs
3/128fs
48
96
kHz
kHz
ns
Low time
ns
Audio Interface Timing
BICK Period
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
(Note 14)
(Note 14)
SDTI Setup Time
Control Interface Timing (3-wire Serial control mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 15)
tF
tSU:STO
tSP
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Cb
pF
MS1010-E-01
2008/10
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
