[AK4359A]
PIN/FUNCTION
No. Pin Name
I/O
I
Function
Master Clock Input
1
MCLK
An external TTL clock should be input on this pin.
Audio Serial Data Clock
DAC1 Audio Serial Data Input
L/R Clock
Reset Mode
2
3
4
5
BICK
SDTI1
LRCK
RSTB
I
I
I
I
When at “L”, the AK4359A is in the reset mode.
The AK4359A must be reset once upon power-up.
Soft Mute in parallel control mode
“H”: Enable, “L”: Disable
Chip Select in serial 3-wire mode
Chip Address in serial I2C mode
Auto Setting Mode in parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Control Data Clock in serial 3-wire mode
Control Data Clock in serial I2C mode
Audio Data Interface Format in parallel control mode
Control Data Input in serial 3-wire mode
Control Data in serial I2C mode
6
7
8
SMUTE
I
CSN
CAD0
ACKS
I
I
I
CCLK
SCL
DIF0
CDTI
SDA
I
I
I
I/O
9
SDTI2
SDTI3
SDTI4
TDM0B
I
I
I
I
DAC2 Audio Serial Data Input
DAC3 Audio Serial Data Input
DAC4 Audio Serial Data Input
10
11
12
TDM I/F Format Mode in parallel control mode
“L”: TDM256 mode, “H”: Normal mode
De-emphasis Filter Enable
Digital Power Supply, +4.5∼+5.5V
Ground
Control Mode Select in serial control mode
“L”: 3-wire Serial, “H”: I2C Bus
De-emphasis Filter Enable in parallel control mode
13
14
15
16
DEM0
DVDD
VSS1
I2C
I
I
DEM1
ROUT4
LOUT4
ROUT3
LOUT3
ROUT2
LOUT2
P/S
I
17
18
19
20
21
22
23
O
O
O
O
O
O
I
DAC4 Rch Analog Output
DAC4 Rch Analog Output
DAC3 Rch Analog Output
DAC3 Rch Analog Output
DAC2 Rch Analog Output
DAC2 Rch Analog Output
Parallel/Serial Select
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
DAC1 Rch Analog Output
DAC1 Lch Analog Output
24
25
26
ROUT1
LOUT1
VCOM
O
O
O
Common Voltage, AVDD/2
Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel with
a 10μF electrolytic cap.
Ground
Analog Power Supply, +4.5∼+5.5V
Data Zero Input Detect
Data Zero Input Detect
27
28
29
30
VSS2
AVDD
DZF2
DZF1
-
-
O
O
Note: All input pins except pull-up pin should not be left floating.
MS1010-E-01
2008/10
- 4 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
