[AK4359A]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4359A, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit = “0”: Register 00H), the sampling speed is set by DFS1-0 bits (Table 1). The frequency of MCLK for
each sampling speed is set automatically. (Table 2~Table 4) In auto setting mode (ACKS bit = “1”: Default), as MCLK
frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6),
it is not necessary to set DFS1-0 bits.
In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4359A
operates by Normal Speed Mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does
not support 128fs and 192fs of double speed mode.
The AK4359A is automatically placed in reset state when the external clocks (MCLK, BICK, LRCK) are stopped during
a normal operation (RSTB pin =“H”). When the external clocks are input again, the AK4359A exit reset state and starts
the operation.
DFS1
DFS0
Sampling Rate (fs)
(default)
0
0
1
0
1
0
Normal Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Double Speed Mode
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
MCLK
512fs
BICK
64fs
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
256fs
384fs
768fs
1152fs
32.0kHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
N/A
N/A
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) (N/A: Not available)
MS1010-E-01
2008/10
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
