ASAHI KASEI
[AK4352]
LRCK
Lch
Rch
BICK
SDATA
16bit
SDATA
18bit
15
14
1
0
Don’t
care
Don’t
care
15
14
1
0
Don’t
care
Don’t
care
15
17
16
3
2
1
0
17
16
3
2
1
0
17
* BICK needs 32fs or 36fs or more than 36fs.
Figure 4. Mode 3 Timing
n
De-emphasis filter
The AK4352 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to 44.1kHz
sampling. The de-emphasis is enabled by setting DEM pin “H”.
n
Power-down
The AK4352 is placed in the power-down mode by bringing PD pin “L” and the anlog outputs are floating(Hi-Z).
Figure 5 shows an example of the system timing at the power-down and power-up.
PD
Internal
State
D/A In
(Digital)
Normal Operation
Power-down
Normal Operation
“0”data
GD (1)
GD (1)
(3)
(2)
(3)
D/A Out
(Analog)
Clock In
MCLK,LRCK,BICK
(4)
External
Mute
(5)
Mute On
Figure 5. Power-down/up sequence example
Notes:
(1) Analog output corresponding to digital input have the group delay (GD).
(2) Analog outputs are floating(Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(“↑
↓”)
of the falling edge of PD signal.
(4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4352 should be in the power-down
mode.
(5) Please mute the analog output externally if the click noise(3) influences system application.
The timing example is shown in this figure.
M0040-E-02
-9-
2000/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
