ASAHI KASEI
[AK4352]
1. Grounding and Power Supply Decoupling
Figure 6 shows the power supply connection example. VDD is supplied from analog supply in system. Decoupling
capacitors for high frequency should be as near to the AK4352 device as possible, with the low value ceramic capacitor
between VREF and VSS being the nearest.
2. Voltage Reference
The differential Voltage between VREF and VSS sets the analog output range. VREF pin is normally connected to VDD.
An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor are attached between VREF and VSS pins. VCML
and VCMR pins are a signal ground of this chip. An electrolytic capacitor less than 10µF parallel with a 0.1µF ceramic
capacitor attached between VCML, VCMR pins and VSS eliminates the effects of high frequency noise. Especially, the
ceramic capacitor should be connected to these pins as near as possible.
No load current may be drawn from VCML and VCMR pins. All signals, especially clocks, should be kept away from the
VREF, VCML and VCMR pins in order to avoid unwanted coupling into the AK4352.
3. Analog Outputs
The analog outputs are single-ended and centeredaround the VCML, VCMR voltage. The output signal range is typically
1.10Vpp. If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the
attenuation by external filter is required. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full
scale for 8000H(@16bit). The ideal output is VCML, VCMR voltage for 0000H(@16bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCML, VCMR
voltage + a few mV.
M0040-E-02
2000/11
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
