ASAHI KASEI
[AK4352]
n System Reset
The AK4352 should be reset once by bringing PD = “L” upon power-up. The internal timing starts clocking by
LRCK “↑” upon exiting reset.
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board [AKD4352] is available in order to allow an easy
study on the layout of a surrounding circuit.
External
Clock
CKS
VCML 15
AOUTL
MCLK
PD
16
1
2
3
4
5
6
7
8
Reset
+
Lch
Out
µ
10
+
+
BICK
SDATA
LRCK
DIF0
14
AK4352
AOUTR 13
VCMR 12
Audio
Data
Processor
+
µ
10
Top View
Rch
Out
VREF
VDD
VSS
11
10
9
DIF1
+
DEM
Mode
µ
µ
10
0.1
Setting
Analog 2V
System Ground
Analog Ground
Figure 6. Typical Connection Diagram
Notes:
- LRCK = fs, BICK ≥ 32fs or 36fs, MCLK = 256fs/384fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
M0040-E-02
2000/11
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
