[AK4344]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7
∼
3.6V; C
L
= 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Frequency
MHz
36.864
4.096
fCLK
Half Speed Mode (512/768/1024/1536fs)
MHz
36.864
2.048
fCLK
Normal Speed Mode (256/384/512/768fs)
MHz
36.864
6.144
fCLK
Double Speed Mode (128/192/256/384fs)
%
60
40
dCLK
Duty Cycle
LRCK Frequency
kHz
24
8
fsh
Half Speed Mode
(DFS1-0 = “10”)
kHz
48
8
fsn
Normal Speed Mode (DFS1-0 = “00”)
kHz
96
48
fsd
Double Speed Mode (DFS1-0 = “01”)
%
55
45
dCLK
Duty Cycle
Audio Interface Timing
BICK Period
ns
1/128fs
tBCK
Half Speed Mode
ns
1/128fs
tBCK
Normal Speed Mode
ns
1/64fs
tBCK
Double Speed Mode
ns
70
tBCKL
BICK Pulse Width Low
ns
70
tBCKH
Pulse Width High
ns
40
tBLR
BICK “↑” to LRCK Edge
ns
40
tLRB
LRCK Edge to BICK “↑”
ns
40
tSDH
SDTI Hold Time
ns
40
tSDS
SDTI Setup Time
Control Interface Timing
CCLK Period
200
ns
tCCK
CCLK Pulse Width Low
80
ns
tCCKL
Pulse Width High
80
ns
tCCKH
CDTI Setup Time
40
ns
tCDS
CDTI Hold Time
40
ns
tCDH
CSN “H” Time
150
ns
tCSW
150
ns
CSN “↓” to CCLK “↑”
tCSS
50
ns
tCSH
CCLK “↑” to CSN “↑”
45
ns
tDCD
CDTO Delay
70
ns
tCCZ
CSN “↑” to CDTO Hi-Z
Power-Down & Reset Timing
PDN Pulse Width
tPD
4
ms/μF
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4344 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C.
When C = 4.7μF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1μF
≤
C
≤
10μF.
When the states of DIF1-0 pins change, the AK4344 should be reset by PDN pin.
MS0641-E-01
-8-
2010/09
AKM [ ASAHI KASEI MICROSYSTEMS ]
