ASAHI KASEI
[AK4348]
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 16. The AK4348 can be reset by bringing RSTB pin = “L”.
Note 17. I
2
C is a registered trademark of Philips Semiconductors.
Timing Diagram
1/fCLK
VIH
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs
VIH
VIL
LRCK
tBCK
VIH
VIL
tBCKH
tBCKL
BICK
Clock Timing
LRCK
tBLR
tLRB
VIH
VIL
BICK
tSDS
tSDH
VIH
VIL
SDTI
VIH
VIL
Audio Serial Interface Timing
MS0532-E-00
-8-
2006/07