ASAHI KASEI
[AK4348]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7
∼
3.6V; C
L
= 20pF)
Parameter
Symbol
Min
fCLK
2.048
Master Clock Frequency
Duty Cycle
dCLK
40
LRCK Frequency
Normal Mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
TDM256 mode (TDM0= “1”, TDM1= “0”)
Normal Speed Mode
fsn
8
High time
tLRH
1/256fs
Low time
tLRL
1/256fs
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
fsn
8
Double Speed Mode
60
fsd
High time
1/128fs
tLRH
Low time
1/128fs
tLRL
Audio Interface Timing
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
tBLR
20
BICK “↑” to LRCK Edge
(Note 14)
tLRB
20
LRCK Edge to BICK “↑”
(Note 14)
tSDH
10
SDTI Hold Time
tSDS
10
SDTI Setup Time
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN High Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
2
Control Interface Timing (I C Bus mode):
-
fSCL
SCL Clock Frequency
1.3
tBUF
Bus Free Time Between Transmissions
0.6
tHD:STA
Start Condition Hold Time (prior to first clock pulse)
1.3
tLOW
Clock Low Time
0.6
tHIGH
Clock High Time
0.6
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling
(Note 15)
0.1
tSU:DAT
SDA Setup Time from SCL Rising
-
tR
Rise Time of Both SDA and SCL Lines
-
tF
Fall Time of Both SDA and SCL Lines
0.6
tSU:STO
Setup Time for Stop Condition
0
tSP
Pulse Width of Spike Noise Suppressed by Input Filter
-
Cb
Capacitive load on bus
Reset Timing
RSTB Pulse Width
(Note 16)
tRST
150
Typ
11.2896
Max
36.864
60
Units
MHz
%
48
96
192
55
48
kHz
kHz
kHz
%
kHz
ns
ns
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48
96
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
µs
µs
µs
µs
µ
s
µ
s
µs
µs
µs
µs
ns
pF
ns
MS0532-E-00
-7-
2006/07
AKM [ ASAHI KASEI MICROSYSTEMS ]
