[AK4183]
[Data Validity]
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 6. Bit Transfer on the I2C-Bus
[ACKNOWLEDGE]
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4183 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, the AK4183 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the
STOP condition.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
S
clock pulse for
acknowledgement
1
2
8
9
START
CONDITION
Figure 7. Acknowledge
MS0500-E-01
9
2008/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
