[AK4183]
DC CHARACTERISTICS (Logic I/O)
(Ta = -40 to 85°C, VCC = 2.5V to 3.6V)
Parameter
Symbol
min
“H” level input voltage
VIH
0.7xVCC
“L” level input voltage
VIL
Input Leakage Current
IILK
-10
VOH
VCC-0.4
“H” level output voltage (PENIRQN pin@ Iout = -250μA)
“L” level output voltage (PENIRQN pin @ Iout = 250μA)
VOL
(SDA pin @ Iout = 3mA)
Tri-state Leakage Current
All pins except for XP, YP, XN, YN pins
IOLK
-10
XP, YP, XN, YN pins
-50
typ
-
-
max
0.3xVCC
10
0.4
10
50
Units
V
V
μA
V
V
μA
μA
SWITCHING CHARACTERISTICS
(Ta = -40 to 85°C, VCC = 2.5V to 3.6V)
Parameter (I
2
C Timing)
Symbol
min
SCL clock frequency
fSCL
30
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock
tHD:STA
0.6
pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
1.3
SDA Hold Time from SCL Falling
2)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed
tSP
0
By Input Filter
Capacitive load on bus
Cb
typ
max
400
Units
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
0.3
0.3
50
400
Note 2. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
SDA
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
VIL
SCL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
VIH
VIL
Figure 1. AK4183 Timing Diagram
MS0500-E-01
5
2008/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
