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AK4127 参数 Datasheet PDF下载

AK4127图片预览
型号: AK4127
PDF下载: 下载PDF文件 查看货源
内容描述: 192kHz的/ 24Bit的高性能异步SRC [192kHz / 24Bit High Performance Asynchronous SRC]
分类和应用:
文件页数/大小: 29 页 / 538 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4127]  
OPERATION OVERVIEW  
System Clock & Audio Interface Format for Input PORT  
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK  
(Mode 0 3 of Table 2) or IBICK (Mode 4 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And  
an internal system clock is created by IMCLK (Mode 8 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0  
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =  
“L”. When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the  
TDM mode at the output port.  
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.  
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in  
BYPASS mode, both IBICK and OBICK are fixed to 64fs.  
Mode IDIF2 IDIF1 IDIF0  
SDTI Format  
ILRCK IBICK  
IBICK Freq  
Master / Slave  
Slave  
0
1
2
3
4
5
6
7
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
16bit, LSB justified  
20bit, LSB justified  
24/20bit, MSB justified  
24/16bit, I2S Compatible  
24bit, LSB justified  
24bit, MSB justified  
24bit, I2S Compatible  
32fsi  
40fsi  
48fsi  
Input  
Input  
L
48fsi or 32fsi  
H
H
H
H
48fsi  
64fs  
64fs  
Output Output  
Reserved  
Master  
Table 1. Input Audio Interface Format (Input PORT)  
SMUTE  
(Note 14)  
Mode  
Master / Slave  
PLL2  
PLL1  
PLL0  
ILRCK Freq  
IBICK Freq  
IMCLK  
0
1
2
3
L
L
L
L
L
L
H
H
L
H
L
8k 96kHz  
Manual  
Depending  
on IDIF2-0  
(Note 11)  
Not  
needed.  
(Note 13)  
8k 216kHz  
16k 216kHz  
(Note 10)  
Semi-Auto  
Manual  
Slave  
H
IMCLK = DVSS  
IBICK = Input  
ILRCK = Input  
32fsi  
(Note 12)  
64fsi  
128fsi  
64fsi  
4
H
L
L
Not  
needed.  
(Note 13)  
8k 216kHz  
(Note 11)  
Manual  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
Semi-Auto  
Manual  
8k 216kHz  
8k 108kHz  
8k 54kHz  
8k 216kHz  
8k 216kHz  
8k 108kHz  
8k 54kHz  
8k 216kHz  
128fsi  
256fsi  
512fsi  
128fsi  
192fsi  
384fsi  
768fsi  
192fsi  
L
Master  
H
H
L
L
H
H
IMCLK = Input  
IBICK = Output  
ILRCK = Output  
Semi-Auto  
Manual  
L
64fsi  
H
H
H
H
Semi-Auto  
Table 2. PLL Setting (Input PORT)  
Note 10. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.  
Note 11. The IBCIK must be continuous except when the clocks are changed.  
Note 12. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.  
Note 13. Fixed to DVSS.  
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.  
MS0593-E-01  
2007/07  
- 13 -