[AK4127]
Input PORT (Master mode)
IBICK Frequency
fBCK
dBCK
tMBLR
tSDH
64fs
50
Hz
%
IBICK Duty
IBICK “↓” to ILRCK
−20
15
20
ns
ns
ns
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Output PORT (Slave mode)
OBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
tSDS
15
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
1/256fs
1/128fs
1/64fs
27
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
(Note 8)
(Note 8)
20
tBLR
20
OLRCK to SDTO (MSB) (Except I2S mode)
OBICK “↓” to SDTO
tLRS
20
20
tBSD
Output PORT (TDM slave mode)
OBICK Period
tBCK
tBCKL
tBCKH
tLRB
81
32
32
20
20
ns
ns
ns
ns
ns
ns
ns
ns
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to BICK “↑”
OBICK “↑” to LRCK Edge
OBICK “↓” to SDTO
TDMIN Hold Time
(Note 8)
(Note 8)
tBLR
tBSD
20
tSDH
tSDS
20
10
TDMIN Setup Time
Output PORT (Master mode)
OBICK Frequency
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
−20
−20
20
20
ns
ns
Reset Timing
PDN Pulse Width
(Note 9)
tPD
150
ns
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4127 can be reset by bringing the PDN pin = “L”.
MS0593-E-01
2007/07
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
