[AK4127]
ILRCK
0
1
2
8
9
24
31 0
1
2
8
9
24
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care 23
23:MSB, 0:LSB
8
1
0
Don't Care 23
8
1 0
Lch Data
Rch Data
Figure 5. Mode 4 Timing
■ System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the
PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the TDM
mode at the output port. The OMCLK pin changes to TDMIN pin for TDM data input in TDM mode.
CMODE CMODE
Mode
CMODE0
Master / Slave
OMCLK
fso
2
L
L
L
L
1
L
L
H
H
0
1
2
3
L
H
L
Master
Master
Master
Master
256fso
384fso
512fso
8k ∼ 108kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 54kHz
H
768fso
Not used. Set to DVSS.
(Note 15)
128fso
Not used. Set to DVSS.
(Note 15)
4
5
6
7
H
H
H
H
L
L
L
H
L
Slave
Master
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
H
H
Slave (Bypass)
H
Master (Bypass) Not used. Set to DVSS.
Note 15. Changed to TDMIN pin when PLL2-0 pins = “L/H/H”.
Table 3. Master/Slave Control (Output PORT)
Mode ODIF1 ODIF0
SDTO Format
LSB justified
(Reserved)
0
1
2
3
L
L
H
H
L
H
L
MSB justified
H
I2S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
MS0593-E-01
2007/07
- 15 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
