[AK4122A]
■ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
BICK
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
SDTO
SDTI
tLRS
tBSD
50%DVDD
tSDS
tSDH
VIH
VIL
Audio Interface Timing (Slave mode)
Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1,
LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as
input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
MS1076-E-01
2010/05
- 12 -