[AK4122A]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
tCLKL
tCLKH
8.192
36.864
MHz
ns
Pulse Width Low
0.4/fCLK
0.4/fCLK
Pulse Width High
LRCK for Input data (LRCK1, LRCK2)
Frequency
ns
fs
Duty
8
48
96
52
kHz
%
Duty Cycle
50
LRCK for Output data (LRCK, LRCK2)
Frequency
Duty Cycle
(Note 10)
fs
32
48
96
52
kHz
%
Slave Mode
Duty
Duty
50
50
Master Mode
%
S/PDIF Clock Recover Frequency
Audio Interface Timing
Input for PORT1
fPLL
32
96
kHz
BICK1 Period
tBCK
tBCKL
tBCKH
tLRB
1/64fs
65
ns
ns
ns
ns
ns
ns
ns
BICK1 Pulse Width Low
Pulse Width High
65
LRCK1 Edge to BICK1 “↑”
BICK1 “↑” to LRCK1 Edge
SDTI Hold Time from BICK1 “↑”
SDTI Setup Time to BICK1 “↑”
Input for PORT2 (Slave mode)
BICK2 Period
(Note 11)
(Note 11)
30
tBLR
30
tSDH
tSDS
30
30
tBCK
tBCKL
tBCKH
tLRB
1/64fs
65
ns
ns
ns
ns
ns
ns
ns
BICK2 Pulse Width Low
Pulse Width High
65
LRCK2 Edge to BICK2 “↑”
BICK2 “↑” to LRCK2 Edge
SDTIO Hold Time from BICK2 “↑”
SDTIO Setup Time to BICK2 “↑”
(Note 11)
(Note 11)
30
tBLR
30
tSDH
tSDS
30
30
Output for PORT2 (Slave mode)
BICK2 Period
tBCK
tBCKL
tBCKH
tLRB
1/64fs
65
ns
ns
ns
ns
ns
ns
ns
BICK2 Pulse Width Low
Pulse Width High
65
LRCK2 Edge to BICK2 “↑”
BICK2 “↑” to LRCK2 Edge
(Note 11)
(Note 11)
30
tBLR
30
LRCK2 to SDTIO (MSB) (Except I2S mode)
tLRS
30
30
BICK2 “↓” to SDTIO
tBSD
Note 10. Min value is 8kHz at BYPASS mode.
Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge.
BICK2 rising edge must not occur at the same time as LRCK2 edge.
MS1076-E-01
2010/05
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
