[AK4122A]
Parameter
Output for PORT3 (Slave mode)
Symbol
min
typ
max
Units
BICK Period
tBCK
tBCKL
tBCKH
tLRB
1/64fs
65
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
65
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
(Note 11)
(Note 11)
30
tBLR
30
LRCK to SDTO (MSB) (Except I2S mode)
tLRS
30
30
BICK “↓” to SDTO
tBSD
Output for PORT2 (Master mode)
BICK2 Frequency
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
BICK2 Duty
BICK2 “↓” to LRCK2
BICK2 “↓” to SDTIO
Output for PORT3 (Master mode)
BICK Frequency
−20
−20
20
30
ns
ns
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
−20
−20
20
30
ns
ns
Control Interface Timing
CCLK Period
(Note 12)
tCCK
tCCKL
tCCKH
tCDS
200
80
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
80
40
tCDH
tCSW
tCSS
40
CSN “H” Time
150
50
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
tCSH
50
tDCD
tCCZ
45
70
CSN “↑” to CDTO Hi-Z
Reset Timing
PDN Pulse Width
(Note 13)
tPD
150
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. In case of using INT2. When INT2 is not used, the max value is not limited.
Note 13. The AK4122A can be reset by bringing the PDN pin = “L”.
MS1076-E-01
2010/05
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
