5
4
3
2
1
CN3
INT0
INT1
D
C
B
A
D
C
B
A
IIC
CN4
U7
CN2
32
49
1
2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DVDD
CM0/CDTO/CAD1
CM1/CDTI/SDA
OCKS1/CCLK/SCL
OCKS0/CSN/CAD0
MCKO1
+
C19
10u
C20
0.1u
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DVSS
TVDD
V/TX
10u
C21
0.1u
C22
+
3
TVDD
AVDD
P/SN
4
V/TX
P/SN
C23
C24
5
XTI
5p
5p
X1
6
XTO
MCKO2
11.2896MHz
7
PDN
DAUX
R61
8
R
BICK
15k
9
AVDD
AVSS
RX1
SDTO
RX1
+
C25
10u
C26
0.1u
10
11
12
13
14
15
LRCK
TXO
V/TX
INT0
INT0
IIC
RX2
JP20
RX21
I2C
TVDD
JP19
3
TVDD
2
2
RX2/DIF0
RX3/DIF1
RX4/DIF2
RX5
FS96/I2C
P/SN
DI3F0
RX31
FS96
1
JP21
2
P/SN
INT1
DI3F1
RX41
RX3
JP22
2
INT1
DI3F2
JP23
RX6
3
1
JP24
2
RX6/IPS
IPS
3
IPS/RX4
RX4
2
FS96
1
IPS
AK4113
JP25
JP26
DIF0
RX5
DIF1
RX6
Title
CN1
AKD4113-B
Size
A3
Document Number
R ev
1
SUB
Date:
Tuesday, November 30, 2004
Sheet
1
3
o f
3
5
4
3
2