ASAHI KASEI
[AK4112A]
n Register Map
Addr Register Name
D7
0
D6
D5
CM1
CS12
DIF1
AUDION
CRC
CA5
D4
D3
D2
D1
D0
00H Clock & Power down Control
01H Input/Output Control
BCU
CM0 OCKS1 OCKS0 PWN
RSTN
MPAR MSTC
TXE
DIF0
IPS1
IPS0
OPS1
OPS0
DFS
02H Format & De-emphasis Control V/TX
DIF2
0
DEAU DEM1 DEM0
03H Receiver status 1
ERF
CV
AUTO
UNLOCK
PEM
V
FS1
FRERR
CA2
FS0
BIP
RFS96
PAR
04H Receiver status 2
STC
CA6
CA14
CA22
CA30
CB6
CB14
CB22
CB30
PC6
05H Channel A Status Byte 0
06H Channel A Status Byte 1
07H Channel A Status Byte 2
08H Channel A Status Byte 3
09H Channel B Status Byte 0
0AH Channel B Status Byte 1
0BH Channel B Status Byte 2
0CH Channel B Status Byte 3
0DH Burst Preamble Pc Byte 0
0EH Burst Preamble Pc Byte 1
0FH Burst Preamble Pd Byte 0
10H Burst Preamble Pd Byte 1
11H Count Control
CA7
CA15
CA23
CA31
CB7
CB15
CB23
CB31
PC7
CA4
CA12
CA20
CA28
CB4
CA3
CA11
CA19
CA27
CB3
CB11
CB19
CB27
PC3
CA1
CA9
CA17
CA25
CB1
CB9
CB17
CB25
PC1
CA0
CA8
CA16
CA24
CB0
CA13
CA21
CA29
CB5
CA10
CA18
CA26
CB2
CB13
CB21
CB29
PC5
CB12
CB20
CB28
PC4
CB10
CB18
CB26
PC2
CB8
CB16
CB24
PC0
PC15
PD7
PC14
PD6
PD14
0
PC13
PD5
PC12
PD4
PC11
PD3
PD11
0
PC10
PD2
PC9
PC8
PD1
PD9
PD0
PD15
0
PD13
0
PD12
0
PD10
EFH1
PD8
EFH0 XFS96
Notes:
For addresses from 12H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
MS0020-E-00
2000/3
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
