ASAHI KASEI
[AK4112A]
n Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C0/1 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. The CSN and CCLK must be fixed to “H” when the register does not
be accessed. PDN= “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4112A
should be reset by PDN= “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
CDTO
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
READ
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
CDTO
D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 10. Control I/F Timing
MS0020-E-00
2000/3
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AKM [ ASAHI KASEI MICROSYSTEMS ]
