ASAHI KASEI
[AK4101A]
n Register Map
Addr
Register Name
D7
CRCE
V4
D6
DIF2
V3
D5
DIF1
V2
D4
DIF0
V1
D3
CKS1
FS3
D2
CKS0
FS2
D1
MUTEN
FS1
D0
RSTN
FS0
00H Clock/Format Control
01H Validity/fs Control
Ch 1 A-channel C-bit
buffer for Byte 0
Ch 1 A-channel C-bit
buffer for Byte 1
Ch 1 A-channel C-bit
buffer for Byte 2
Ch 1 A-channel C-bit
buffer for Byte 3
02H
CA7
CA15
CA23
CA31
CA6
CA14
CA22
CA5
CA13
CA21
CA4
CA12
CA20
CA3
CA11
CA19
CA2
CA10
CA18
CA1
CA9
CA0
CA8
03H
04H
CA17
CA16
CA24
05H
CA30
…
CA29
…
CA28
…
CA27
…
CA26
…
CA25
…
CB7
…
CB31
UA7
…
UA31
UB7
…
CB0
…
CB24
UA0
…
UA24
UB0
…
06H-
09H
Ch 1 B-channel C-bit
buffer for Byte 0-3
…
…
…
…
…
…
…
…
…
…
…
…
0AH-
0DH
Ch 1 A-channel U-bit
buffer for Byte 0-3
…
…
…
…
…
…
…
…
…
…
…
…
0EH-
11H
Ch 1 B-channel U-bit
buffer for Byte 0-3
UB31
…
…
…
…
…
…
UB24
12H-
15H
16H-
19H
1AH-
1DH
1EH-
21H
22H-
25H
26H-
29H
2AH-
2DH
2EH-
31H
32H-
35H
36H-
39H
Ch 2 A-channel C-bit
buffer for Byte 0-3
Ch 2 B-channel C-bit
buffer for Byte 0-3
Ch 2 A-channel U-bit
buffer for Byte 0-3
Ch 2 B-channel U-bit
buffer for Byte 0-3
Ch 3 A-channel C-bit
buffer for Byte 0-3
Ch 3 B-channel C-bit
buffer for Byte 0-3
Ch 3 A-channel U-bit
buffer for Byte 0-3
Ch 3 B-channel U-bit
buffer for Byte 0-3
Ch 4 A-channel C-bit
buffer for Byte 0-3
Ch 4 B-channel C-bit
buffer for Byte 0-3
Ch 4 A-channel U-bit
buffer for Byte 0-3
Ch 4 B-channel U-bit
buffer for Byte 0-3
…
…
…
…
…
…
…
…
…
…
…
…
3AH-
3DH
3EH-
41H
Table 7. Register Map
Notes:
(1) In stereo mode, A indicates Left Channel and B indicates Right Channel.
(2) In asynchronous mode, the DIF2-0 and CKS1-0 bits are logically “ORed” with the DIF2-0 and CKS1-0 pins.
(3) For addresses from 42H to FFH, data is not written.
(4) The PDN pin = “L” resets the registers to their default values.
MS0250-E-00
2003/07
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
