ASAHI KASEI
[AK2572]
L
Table 5-1 EEPROM Address Space in Power Leveling [1]
RE_MODV_SEL
1
0
MOD_CTRL-pin
H
L
H
EEPROM
E_MOD_TC [2]
E_MOD_TC [1]
E_BIAS_TC
Device Address
Address
00h ~ 7Dh [*]
00h ~ 7Fh
80h ~ FFh
00h ~ 1Fh
DAC
－
－
A0h
A4h
A4h
A6h
V-DAC3
－
I-DAC1
－
V-DAC3
I-DAC2
I-DAC1
I-DAC1
I-DAC2
V-DAC3
I-DAC2
I-DAC1
I-DAC2
V-DAC3
E_EXTRA_TC
[*] Since Write Protect control register is allocated at “Device Address＝A0h / Address＝7Eh, 7Fh”, E_MOD_TC
[2] has 126 address locations. Therefore E_MOD_TC [2] has 2 fewer address locations as compared with
E_MOD_TC [1] and E_BIAS_TC. So the linear interpolation of E_MOD_TC [2] is executed as follows :
R_MOD_FF(z)＝E_MOD_TC2(x－1)＋｛E_MOD_TC2(x)－E_MOD_TC2(x－1)｝×R_TEMP [0] / 2
when z＝R_TEMP [7:0]＝0 ~ 5, E_MOD_TC(x)＝E_MOD_TC(x－1)＝E_MOD_TC(0)
where the detected temperature data is R_TEMP [7:0]＝z＝2x+5,2x+4, R_TEMP [7:1]＝x, E_MOD_TC[2] as
E_MOD_TC2(x) and the obtained data by a linear interpolation is R_MOD_FF(z).
5. 2 Power Leveling [2]
In Power Leveling [2] mode, the data to be loaded to register (R_BIAS_FF, R_MOD_FF) can be selected by
R_PWR_SEL setting among 4 patterns of Bias current and Modulation current temperature compensation
data that are retained in EEPROM.
Power Leveling [2] is enabled by setting RE_PWR_LVL1_SET＝“0” and RE_PWR_LVL2_SET＝“1”.
When the write protect is released (WP-pin＝“H” and R_WP_CTRL＝“0”), R_PWR_SEL [1:0] data at “Device
Address＝A8h / Address＝2Fh” can be altered in Self-Operation Mode.
When Power Leveling [2] is enabled, a linear interpolation of the temperature compensation data is executed by
using R_TEMP [7:3], R_TEMP [2:0] and the data in EEPROM as shown in Table 5-2.
R_BIAS_FF(z)＝E_BIAS_TCn(y－1)＋｛E_BIAS_TC n(y)－E_BIAS_TCn(y－1)｝×R_TEMP [2:0] / 8
R_MOD_FF(z)＝E_MOD_TCn(y－1)＋{E_MOD_TCn(y)－E_MOD_TCn(y－1)}×R_TEMP [2:0] / 8
when y＝0 (R_TEMP [7:0]＝z＝0~7), E_BIAS_TCn(y)＝E_BIAS_TCn(y－1)＝E_BIAS_TCn(0) and
E_MOD_TCn(y)＝E_MOD_TCn(y－1)＝E_MOD_TCn(0).
where the detected temperature data R_TEMP [7:0]＝z＝8y, 8y+1, ・・・, 8y+7, R_TEMP [7:3]＝y, the
temperature compensation data retained in EEPROM is E_BIAS_TCn(y), E_MOD_TCn(y), n＝0~3 and the
obtained data by a linear interpolation is R_BIAS_FF(z), R_MOD_FF(z) respectively.
Table 5-2 EEPROM Address Space in Power Leveling [2]
RE_ PWR_LVL2_SET＝”0”
R_TEMP ［7:1］
RE_ PWR_LVL2_SET＝”1”
R_TEMP ［7:3］
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
00h ~ 1Fh
Data
Address
RE_PWR_SEL
Data
Address
0
1
2
3
0
1
2
3
E_MOD0_TC 00h ~ 1Fh
E_MOD1_TC 20h ~ 3Fh
E_MOD2_TC 40h ~ 5Fh
E_MOD3_TC 60h ~ 7Fh
E_BIAS0_TC 80h ~ 9Fh
E_BIAS1_TC A0h ~ BFh
E_BIAS2_TC C0h ~ DFh
E_BIAS3_TC E0h ~ FFh
00h ~ 7Fh E_MOD_TC 00h ~ 7Fh
00h ~ 7Fh E_BIAS_TC 80h ~ FFh
-26-
< MS0290-E-01>
2004/8
AKM [ ASAHI KASEI MICROSYSTEMS ]
