[AK2331]
2.6) VOUT0～VOUT3 Control register
Address
Data
A3
1
A2
1
A1
0
A0
1
D7
−
D6
−
D5
−
D4
−
D3
D2
CTRL2
0
D1
CTRL1
0
D0
CTRL0
0
CTRL3
−
−
−
−
0
Initial Value
Function
Data
Item
Remarks
0
1
CTRL3
to
CTRL 0
VOUT0 to VOUT3
Output control
VOUT［7:0］data is output
VOUT［7:0］data is held
Latch-timing of each DAC data can be matched by the CTRL register setting.
After VOUT[7:0] is set, when CTRL register is set to “0”, VOUT[7:0] data is reflected in the DAC output
immediately.
When CTRL register is set to “1”, DAC output will not be affected regardless of changes made in
VOUT[7:0] data. In this case VOUT[7:0] data output by DAC will remain the same as that of data when
setting CTRL register to “1”. The data will be reflected in the DAC output when the timing is set to “0”.
MS0903-E-00
2008/03
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
